CMOS TECHNOLOGY FOR HIGH SPEED TIME ACCURACY PERFORMANCE APPLICATION IN VLSI

Abstract

High-speed interfaces require testers with high timing accuracy application. However, timing accuracy in an oversampled receiver is limited by numerous error sources. Increasing the sampling resolution requires high-frequency or finely spaced sampling clocks [1]. The maximum frequency of a clock generator is fundamentally limited by the ability to propagate clock pulses through CMOS inverters which are the most basic form of a clock buffer. Static and dynamic variations in the position of clock edges from their ideal locations are a significant obstacle to building high-precision clock generators.

Key Words: CMOS, time Accuracy, Static, Dynamic, DLL, PLL, VCO