A 16bit 31?w Resetting 2nd Order ?? Modulator in 130 nm Technology

Abstract

High-resolution, moderate-speed, calibration-free analog-to-digital converters (ADCs) are becoming increasinglydifficult to design in low-voltage nanometer-scale CMOS processes.We proposedADC architecture based on a resettingmodulator that achieves high resolution, despite poor componentmatching. The design utilized one pipelines a second-order resetting modulator and a10b cyclic ADC. The device achieves 16b resolution. It consumes 31?W from a 1.8 V supply.The whole analysis done in 130nm technology.
Key words: ADC, high-resolution, Resetting ?? modulator, Quantizer, Comparator,D flip- flop, FIR filter.