Analyzing the Implementation of a NoC Performance Simulation Framework

Abstract

NOC architectures are based on packet-switched networks. To extend the applicability of moore’s law, the Multiprocessor architectures and platforms have been introduced. They depend on concurrency and synchronization in both software and hardware to enhance the design productivity and system performance. To design and implement network- on- chip simulation framework for supporting 3-D Mesh, Irregular and 2-D NoC. The simulation framework is proposed to be capable of evaluating the performance of various topology designs and routing function based on popular communication performance matrices such as Latency, Throughput, and Energy etc. Key words: NOC, SOC, IC, Simulation Framework, Mesh.