DR. JAI GOPAL PANDEY, C. R. An Implementation 8×8 circuit of the 6T SRAM Bit cell by using Memory Array. International Journal of Engineering Technology and Computer Research, [S. l.], v. 3, n. 4, 2015. Disponível em: https://ijetcr.org/index.php/ijetcr/article/view/220. Acesso em: 6 aug. 2026.