Design and Analysis of Storage Element using different Technologies

Abstract

Over the past decade, Power consumption of digital systems has been continuously increasing. The need of low power design is becoming a vital parameter in high performance digital systems. This paper enumerates low power , high speed designs of D flip flop. It presents various techniques to minimize the power consumption of the digital circuits. In this paper implementation of D flip flop using CMOS TG(Transmission gates) Technique, GDI(Gate diffusion input ) Technique is presented and compared. The design and simulation is done using Tanner EDA and 180nm technology. In this the proposed designs are best energy efficient and having an efficient improvement in Transistor count and power consumption.
Key Words: Low power, less transistors, D flips flop, TG, GDI