Short Circuit Power Reduction in Schmitt-Trigger Based SRAM Cell Design

Authors

  • 1Madhavi.Sowpati, 2G.Mangarao 1Research Scholar, VLSI & ES, Malinenilakshmaiah Engineering College, India

Abstract

In low power SRAM Memory cell design power dissipation through standby leakage and dynamic loss is a major problem. This paper is mainly based on low power cell operation and delay of SRAM designing. The paper presents a novel technique to reduce short circuit power. The differential SRAM for ultra low voltage design for Schmitt- Trigger (ST) is analyzed using 180nm cmos technology. Schmitt- Trigger (ST) based differential SRAM cell design helps to sort the issues related to design problems in read and write operation of basic SRAM cell. Feedback is built-in mechanism in proposed Schmitt-Trigger SRAM design. There is always a trade-off among area, power and delay in any SRAM cell designing. In comparison to standard 6T SRAM cell the ST SRAM cell provides better read stability and having a high probability of read failure. Short Circuit power dissipation is one of the considerable parameter in achieving low power. This paper mainly proposes a novel technique for achieving the low power consumption. Delay of an SRAM cell is maintained as it was without affecting the delay with the reduction of power. The read power and write power consumption of an SRAM cell is shown in the following table. By using novel power technique to reduce the short circuit power compared to the proposed design in the paper is reduced by an amount of 21%. The write delay is maintaining constantly even after using the technique to reduce the short circuit power. The performance analysis of the novel design is better than proposed design. Keywords: Static Random Access Memory, Short Circuit Power, Schmitt-Trigger, Ultra-Low Voltage, Built-In Feedback Mechanism, Stability analysis.

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Published

2016-08-30

How to Cite

2G.Mangarao, 1Madhavi.Sowpati,. (2016). Short Circuit Power Reduction in Schmitt-Trigger Based SRAM Cell Design. International Journal of Engineering Technology and Computer Research, 4(4). Retrieved from https://ijetcr.org/index.php/ijetcr/article/view/325

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